Covered0.7.10

Covered is a Verilog code-coverage utility used for Design Verification which is capable of performing line, toggle, memory, combinational logic, finite state machine (FSM) and assertion coverage analysis. Verilog source files are parsed along with VCD/LXT/FST dumpfiles (or can be run as VPI module in the simulator) to create Coverage Description Database (CDD) files which can be merged with other CDD files generated from the same design and/or have reports generated from them through the use of the merge and report commands, respectively.