Structural Verilog compiler for UN*X operating systems. Some synthesizable behavioral constructs are now supported. An event simulator (vsim) is included for testing of logic designs. A cycle simulation compiler (cyco/csim) is included which can compile netlists into fast levelized C code. Cyco can also generate ABEL netlists that may be used for FPGA generation. GTKWave, a fully-featured wave viewer is quite functional now. (requires GTK+-1.2.0 or greater).
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GPL
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1.3.36-2
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