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| Covered - Verilog code coverage analysis utility.Updated by trevorw on Sunday, October 25th 2009. Covered is a Verilog code-coverage utility used for Design Verification which is capable of performing line, toggle, memory, combinational logic, finite state machine (FSM) and assertion coverage analysis. Verilog source files are parsed along with VCD/LXT dumpfiles (or can be run as VPI module in the simulator) to create Coverage Description Database (CDD) files which can be merged with other CDD files generated from the same design and/or have reports generated from them through the use of the merge and report commands, respectively. Licence : GPL
Version : 0.7.7 [Stable]20090802 [Development]
Release Notes : Bug fix release.
Platforms : Independent
Requirements : gperf, bison, flex, gcc, GNU make, Tcl/Tk
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