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Ver, Structural Verilog compiler for UNIX operating systems.

Updated by Editors on Sunday, September 29, 2002.

Structural Verilog compiler for UN*X operating systems. Some synthesizable behavioral constructs are now supported. An event simulator (vsim) is included for testing of logic designs. A cycle simulation compiler (cyco/csim) is included which can compile netlists into fast levelized C code. Cyco can also generate ABEL netlists that may be used for FPGA generation. GTKWave, a fully-featured wave viewer is quite functional now. (requires GTK+-1.2.0 or greater).

Dowloads: 3807
GPL
1.3.36-2

Download Latest Ver releases for Linux :

Ver 1.3.36-2
September 29, 2002

Ver Contact / Download Links

Author / maintainer:
Tony Bybell
Web site:
http://linux-workshop.com/bybell/ver/
Alternate download:
ftp://metalab.unc.edu/pub/Linux/Incoming

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